时间：2015年1月7日下午3：00

地点：电气A101

报告人：Yee Hong Leung (龙以康)

1. Round off Errors in Fixed-Point Digital Filters

When operating, the computational module of digital filters performs only multiplications and additions. In most hardware implementations, these arithmetic operations are performed in fixed-point. An immediate issue regarding the implementation of the multiplier is that some form of quantization scheme must be included in the hardware to convert the double-word length product term back to single-word length. The most commonly used quantization schemes are rounding and truncation. However, both schemes will lead to a DC bias in the filter output. In this presentation, we consider a zero-bias quantization scheme, the magnitude rounding scheme, and study the probability distribution and spectral characteristics of the resulting round off errors.

2. On the WLS Design of Variable Fractional Delay Filters

The weighted least-squares design of Farrow-based variable fractional delay filters is known to suffer from numerical difficulties which can lead to design failures. In this presentation, we derive a set of analytical expressions to overcome these difficulties. The analytical expressions also allow us to derive the proofs of a number of properties that previous researchers have claimed regarding the design of variable fractional delay filters. As an aside, this presentation unifies under a common framework the various weighted least-squares design formulations that have been proposed and studied.

报告人简介：

Yee Hong Leung (龙以康) was born in Singapore. He obtained the B.E. (Hons) and Ph.D. degrees, both in electrical engineering, from the University of Western Australia, Australia, in 1977 and 1986, respectively.

He was with the School of Electrical, Electronic and Computer Engineering, the University of Western Australia, as a Tutor from 1982 to 1986 and as a Lecturer from 1988 to 1994. From 1986 to 1988, he was with the Defence Science and Technology Organisation, South Australia as a Research Scientist. In 1994, he joined the Western Australian Telecommunications Research Institute, Curtin University, Australia, as a Senior Research Fellow, and in 2004, he joined the Department of Electrical and Computer Engineering, Curtin University as a Senior Lecturer. His research interests are in filter design, and adaptive, optimum and robust signal processing and their applications in antenna arrays and telecommunication systems.